[Chisel] Dequeuing data from Queue is delayed by one cycle

Phenomenon

The below is my design

1. The ID stage puts the decoded instruction into the Queue

2. EX stage retrieves the instruction from the Queue and executes it

At the first time, one cycle is required between putting the first command in the Queue with 1 and taking it out with 2.

The EX stage is always empty at first, so I want to take it out as soon as ID stage puts into the queue.

Cause

This is a Queue specification; if there is no instruction, deq.valid becomes false and it cannot be retrieved.

Since "instruction is put" is reflected from the next cycle, it seems that one extra cycle is required.

  io.deq.valid := !empty

Solution

The solution is to set flow = true in the Queue constructor argument (it is false by default).

If flow is true, valid is set to true

  if (flow) {
    when(io.enq.valid) { io.deq.valid := true.B }
  }

Reference

https://github.com/chipsalliance/chisel/blob/main/src/main/scala/chisel3/util/Decoupled.scala