RISCV

Jun 29

[Chisel] Block inside "when" is always executed

Phenomenon There is an array Check whether the index variable is within the size of the array, and access the element only if it is...

Jun 29

[Chisel] Queue.enq.valid vs deq.valid

Overview When communicating data using a Queue, the following operations are possible: Queue.io.enq.valid: When set to false, data will...

Jun 29

[Chisel] Don't use polymorphism

What I want to do There are multiple similar units Most of processes are the same, only some differences. Select an appropriate unit...

Jun 29

[Chisel] Exiting a loop

What want to do ★ There are multiple modules of the same type Select one of these that meets the specified condition. To achieve this, I...

Jun 29

[Chisel]What to connect to Bundle is hardware

Phenomenon When I run the following code: class Signals extends Bundle{ val pc = UInt((32.W)) ・・・ } val sig = Wire(new Signals) sig.pc...

Mar 9

[Chisel/Scala] Introduce decimal point data

What I want to do I want to introduce decimal point data (float in other languages). The background is that I'm trying to set up a...

Feb 23

[Chisel] About conditional branching

Introduction While writing chisel, you will learn that you can use the following syntax as a conditional branch. if when Mux (MuxCase)...

Feb 23

[scala/chisel] value >> is not a member of (chisel3.Bool, chisel3.UInt)

Issue The following code causes the compilation error in the title val x = 3.U(16.W) val y = 5.U(16.W) val mul_out := MuxCase(0.U(16.W),...

Feb 23

[Chisel] Casting integer type

Want I want to do I want to expand a chisel.UInt type variable defined in 32bit to 64bit. What is impossible First, the following will...

Feb 3

[RISCV/Chisel]Error: unrecognized opcode vsetvli

Situation I'm Implementing RISCV vector instructions with chisel. When adding the vsetvli instruction, the above compilation error...