[Chisel]What to connect to Bundle is hardware

Phenomenon

When I run the following code:

class Signals extends Bundle{
  val pc = UInt((32.W))
  ・・・
}

val sig = Wire(new Signals)
sig.pc := 0.U

The following error occurs:

chisel3.package$ExpectedHardwareException: data to be connected 'UInt' must be hardware, not a bare Chisel type. Perhaps you forgot to wrap it in Wire() or IO()?

Causes and Solutions

As the error message says, you must have hardware connected to sig.pc. To do this:

sig.pc := WireDefault(0.U)

At first I thought, "Bundle is just a collection of data" and confused to connect hardware.

After some thoughts I reached a conclusion that Bundle is a group of signal lines that are connected simultaneously.

So I tried to define it as follows, but it gave me a compilation error.

class Signals extends Bundle{
  val pc = Wire(UInt((32.W)))
  ・・・
}

In the end, a Bundle is a definition of "how to interpret the values of each signal line," so it seems best to interpret it as a chisel type rather than a hardware type (although it is hardware that is actually connected).