[Chisel/scala] Adding a hardware array to a bundle member

What want to do

As the title says, I want to add a chisel hardware array to a Bundle member. Situation is tat I want to implement multiple identical circuits and process them in parallel.

It's easy if it's an array of UInt, but I had a lot of trouble when the members of the array are hardware.

Premise

• There are Scala types, chisel types, and chisel hardware.

  • Int and Seq are Scala types

  • UInt and Vec are chisel types

  • Wire and Reg are hardware

• Only chisel types can be added to Bundle members.

  • reference

How to do

Based on the above, the array should be a Vec, not a Seq.

So first I tried writing it like this:

class MyParts extends Module{
  ・・・
}

class MyBundle extends Bundle{
  val myVec :Vec[MyParts] = VecInit(4)(new Wire(MyParts))
}

This will result in the following error:

chisel3.package$ExpectedChiselTypeException: Bundle: MyBundle contains hardware fields: 

Since it was initialized with Wire(), the compiler recognized it as chisel hardware and gave me an error.

So when I remove the Wire, I get an error that says "Attach Wire"

vec element 'MyClass' must be hardware, not a bare Chisel type. Perhaps you forgot to wrap it in Wire(_) or IO(_)?

Hmm...

The arguments to VecInit must be hardware, but the members of a Bundle cannot be hardware...

So I wrote the following and got no compilation errors:

class MyBundle extends Bundle{
  val myVec :Vec[MyParts] = Vec(4, new MyParts)
}

The likely causes are speculated to be as follows:

• VecInit() initializes a Vec with specific values. Therefore, it requires specific "hardware" as an argument.

• Vec() initializes Vec with default values. Therefore (?), the arguments are not limited to hardware.

Honestly, the logic around '?' is unclear, so I can't say with any confidence...

Summary

class MyBundle extends Bundle{
  val myVec :Vec[MyParts] = Vec(4, new MyParts)
}

This is not officially stated, but simply means that if you do it this way, no errors will occur.